1. Field of the Invention
The present invention relates to a method for controlling a time point for data output in a synchronous memory device, and more particular to a method for controlling a time point for data output in a synchronous memory device according to CAS latency.
2. Description of the Prior Art
As generally known in the art, a memory device such as a DDR SDRAM generates a plurality of control signals (e.g., OE00, OE10, OE30, and OE50 shown in FIG. 1E) used for controlling the operation of a data output driver according to CAS latency. Conventionally, these control signals are sequentially generated. In other words, the control signals are generated in the order of OE00, OE10, OE20, OE30, OE40 and OE50. For reference, the OE20 is generated with delay of 1tCK (1tCK is a period of an internal clock signal) as compared with the OE10, the OE30 is generated with delay of 1tCK as compared with the OE20, and the OE40 is generated with delay of 1tCK as compared with the OE30. As can be understood from the above, the OE00 and the OE10 are generated with a time difference of 1tCK, and the OE10 and the OE20 are generated with a time difference of 1tCK. In other words, a time difference between OE signals adjacent to each other is 1tCK. However, as the internal operation frequency of a memory device increases, the time difference may decrease below 1tCK. As the time difference decreases, the control signals (OE signal) sequentially generated with the time difference of 1tCK may collide with each other. This collision may cause malfunction when the memory device outputs data.